1. Field of the Invention
The present invention relates to a processor used in a digital still video camera, a facsimile, a color copying machine, a visual telephone, etc. and performing an orthogonal transformation such as a discrete cosine transformation (which is called a DCT in the following description) and a discrete sine transformation (which is called a DST in the following description) for increasing and decreasing the size of a color image, etc.
2. Description of the Related Art
An orthogonal transformation such as the discrete cosine transformation and the discrete sine transformation is known in one transformation coding method for compressing information.
For example, an image is divided into blocks constructed by (8.times.8) picture elements in a one-dimensional discrete cosine transformation for compressing the image and a one-dimensional inverse discrete cosine transformation (IDCT) for extending the image. In this case, it is necessary to perform 64 multiplying operations and 56 adding operations. Therefore, processing times for performing the discrete cosine transformation and the inverse discrete cosine transformation are increased and circuits for performing these transformations are large-sized so that it is difficult to integrate these circuits.
When a discrete sine transformation instead of the discrete cosine transformation is performed as the orthogonal transformation, a processing time for performing the discrete sine transformation is similarly increased and a circuit for performing this transformation is large-sized.
When input data are constructed by n bits and the number of kinds of transformation coefficients is set to m in a ROM look-up table method, the address space of a ROM is represented by m.times.2.sup.n. When the discrete cosine transformation is performed with respect to the blocks constructed by (8.times.8) picture elements, the number of kinds of the transformation coefficients is fixedly set to 8 and the input data are constructed by eight picture elements each constructed by eight bits. Accordingly, in this case, the number n of bits is equal to 64 and the address space is represented by 8.times.2.sup.64. It is difficult to realize a circuit having such a large capacity.